A New Low-Power Scan-Path Architecture

In this paper, we present a low power architecture for scan-path. This architecture is suitable when it is used with a test compression. Based on data compression methodology, the vector set is partitioned so that the segments repeated in every scan can be removed. Here, it is not needed to change all bits of scan path during the new scan path where new test vector will be filled. In this way, every time that a new test vector should be applied to the circuit, only cells of the scan-path change that their data differs in the new test vector. Therefore, the new test vector is applied to the circuit under test with fewer number of clock cycles. This paper shows a novel scan cell architecture that reduces both power consumption and the total energy using a data compression technique.